1. Field of the Invention
The present invention relates generally to methods for forming split gate field effect transistor device arrays. More particularly, the present invention related to methods for forming split gate field effect transistor device arrays with enhanced areal density.
2. Description of the Related Art
A split gate field effect transistor device employs a floating gate electrode formed over and separated from a semiconductor substrate by a tunneling dielectric layer. The floating gate electrode defines a floating gate electrode channel within the semiconductor substrate. A split gate field effect transistor device further comprises a control gate electrode partially overlapping the control gate electrode and separated therefrom by an intergate electrode dielectric layer. The control gate electrode defines a control gate electrode channel adjoining the floating gate electrode channel within the semiconductor substrate. A split gate field effect transistor device finally comprises a pair of source/drain regions separated by the aggregate of the floating gate electrode channel and the control gate electrode channel.
To operate a split gate field effect transistor device, pre-determined voltages are applied to the control gate electrode, the source region, the drain region and the semiconductor substrate such as to allow for charge injection from the semiconductor substrate in the floating gate electrode, thus providing for nonvolatile charge storage. An additional pre-determined series of voltages may be employed for discharging and reading the stored charge.
While split gate field effect transistor devices provide a particularly common and desirable semiconductor device structure for non-volatile data storage and retrieval, split gate field effect transistor devices are nonetheless not entirely without problems.
In that regard, since split gate field effect transistor devices are fabricated employing plural overlapping gate electrode layers, split gate field effect transistor devices are often difficult to fabricate with enhanced areal density.
It is thus desirable to provide methods for fabricating split gate field effect transistor devices with enhanced areal density. It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed within the semiconductor product fabrication art for forming, with desirable properties, split gate field effect transistor devices. Included but not limiting among the methods are those disclosed within Da et al., in U.S. Pat. No. 6,239,245 (a method for forming a split gate field effect transistor device with a reduced bit-line pitch).
Desirable are additional methods for forming split gate field effect transistor device arrays with enhanced areal density.
It is towards the foregoing object that the present invention is directed.